A 32-bank 256-Mb DRAM with cache and TAG |
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| Authors: | Tanoi S. Tanaka Y. Tanabe T. Kita A. Inada T. Hamazaki R. Ohtsuki Y. Uesugi M. |
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| Affiliation: | Electron. Devices Group, OKI Electr. Ind. Co. Ltd., Tokyo; |
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| Abstract: | ![]()
A 125 megabyte/s synchronous 32-bank 256-Mb DRAM has been developed by a bank-interleaving oriented multibank architecture including a shared-sense amplifier cache with an overlapped bank control for hidden precharge, phase-aligned timing pulse transmission, and voltage controlled negative conductance (VCNC) data-bus current sense amplifier |
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