TCAD and SPICE modeling help solve ESD protection issues in analog CMOS technology |
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| Authors: | D. Tr mouilles, G. Bertrand, M. Bafleur, F. Beaudoin, P. Perdu, N. Guitard,L. Lescouz res |
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| Affiliation: | a ON Semiconductor, 14 rue Paul Mesplé, 31035, Toulouse Cedex, France;b LAAS/CNRS, 7 Avenue Colonel Roche, 31077, Toulouse Cedex, France;c CNES-THALES Laboratory, 18 av. Edouard Belin, 31401, Toulouse Cedex, France |
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| Abstract: | ![]()
The number of circuit design iterations due to electrostatic discharge (ESD) failures increases with the complexity of VLSI technologies and their shrinking. In this paper, we show how TCAD and ESD SPICE modeling can be used to solve ESD protection issues in an analog CMOS technology. |
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