A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-pointnoise reduction coding I/O

A 32-b 500-MHz 4-1-1-1 operation 4-Mb pipeline burst cache SRAM has been developed. In order to achieve both high bandwidth operation and short latency operation, we developed the following technologies: 1) a prefetched pipeline-burst scheme with double late-write buffers, 2) gate size reduction and a bit-line equalization by source resetting, 3) point-to-point bidirectional coding I/O's to reduce bus noise and power consumption, and 4) a three-level metal 0.25-μm CMOS process technology with six transistor memory cells