SOS/CMOS as a High-Performance LSI Device

To realize a high-performance LSI, the devices used should satisfy the following requirements: 1) high-speed operation, 2) low power consumption, 3) easy designability, and 4) high integration capability. SOS/CMOS has been examined both experimentally and theoretically for these aspects. Ideal CMOS operation with /spl tau//sub pd/ ~ 100 ps with 0.1-pJ energy required to switch an inverter is obtained. 1-GHz operation is confirmed on dynamic 1/16 frequency dividers with 1.0-/spl mu/m effective channel-length devices. Using the same device, a maximum multiplying time, /spl tau//sub mul/ ~ 25 ns at 5 V with 15-mW average power at 10/sup 7/ multiplications/s is obtained on a 4 X 4 parallel multiplier. The above result agrees with circuit simulation predictions without including stray capacitance associated with the wiring. The same simulation predicts rmul ~ 60 ns with a maximum power dissipation of 200 mW at 16-MHz operation for a 16 X 16 parallel multiplier. This prediction is also confirmed experimentally. These facts indicate good designability of SOS/CMOS. For larger scale integration capability estimation, power dissipation and wiring delay were examined theoretically for bulk NMOS, bulk CMOS, and SOS/CMOS. The results indicate that for smaller scale integration, bulk NMOS and SOS/CMOS operate faster than bulk CMOS. However, for larger scale integration, SOS/CMOS operates faster than bulk CMOS which, in turn, operates faster than bulk NMOS.