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二维级联流水结构大点数FFT运算器实现研究
引用本文:王晓君,龙腾,周希元. 二维级联流水结构大点数FFT运算器实现研究[J]. 无线电工程, 2010, 40(11): 19-22
作者姓名:王晓君  龙腾  周希元
作者单位:[1]石家庄市通信测控技术研究所博士后工作站,河北石家庄050081 [2]北京理工大学博士后流动站,北京100081 [3]河北科技大学信息科学与工程学院,河北石家庄050018
摘    要:大点数快速傅里叶变换(FFT)运算在雷达、通信信号侦察中有广泛应用,其基于现场可编程门阵列(FPGA)的实现方法有重要的研究价值。推导出点数为N的大点数FFT运算分解为2级小点数FFT运算级联的运算公式,在此基础上给出其实现步骤,从流水线结构设计、基本运算单元以及地址生成等方面详细介绍一维列(行)变换的工程实现方法,并给出列、行变换之间所乘旋转因子的压缩算法。工程实际应用表明,该大点数FFT运算器具有变换速度快、调试方便及可在单片FPGA实现的优点。

关 键 词:FFT运算器  级联  流水  工程实现

Research on Implementation of 2-dimension Long FFT Processor Based on Cascade-pipelined Structure
WANG Xiao-jun,LONG Teng,ZHOU Xi-yuan. Research on Implementation of 2-dimension Long FFT Processor Based on Cascade-pipelined Structure[J]. Radio Engineering of China, 2010, 40(11): 19-22
Authors:WANG Xiao-jun  LONG Teng  ZHOU Xi-yuan
Affiliation:1.Post-doctor Workstation of the 54th Research Institute of CETC,Shijiazhuang Hebei 050081,China;2.Post-doctor Exchange Station of Beijing Institute of Technology,Beijing 100081,China;3.College of Information Science & Engineering,Hebei University of Science & Technology,Shijiazhuang Hebei 050018,China)
Abstract:Long fast Fourier transform(FFT)processor is widely applied,and its implementation based on field programmable gate array(FPGA)has a great research value.The equations of N-point long FFT operating being divided into stage cascading of 2 smaller points FFT is firstly derived,and its implementation steps are presented at same time.And then the implementation methods in engineering of 1-dimension column(row)transform is introduced in detail from aspects on design of pipeline structure,basic operating unit and address generating and so on.At last,the compress algorithm of twiddle factors between column transform and row transform is discussed.It is proved in practical engineering this long FFT processor has the advantages of high speed,easy debug and implementing on single FPGA chip.
Keywords:FFT processor  cascaded  pipelined  engineering implementation
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