Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs |
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| Affiliation: | 1. Department of Electrical Engineering, National Taiwan Normal University, Taiwan;2. Institute of Electronics, National Chiao Tung University, Taiwan;1. Shenzhen Key Laboratory of Electromagnetic Control, Shenzhen University, Shenzhen 518060, China;2. Guangdong Key Laboratory of Optomechatronics Integration, Research Institute of Tsinghua University in Shenzhen, Shenzhen 518057, China;1. Delft Institute of Microsystems and Nanoelectronics, Delft University of Technology, Delft 2628 CD, The Netherlands;2. Changzhou Institute of Technology Research for Solid State Lighting, Changzhou 213161, China;3. Beijing Solid State Lighting S&T Promotion Center, Beijing 100083, China;4. Key Laboratory of Optoelectronic Technology & Systems, Education Ministry of China, Chongqing University, Chongqing 400044, China;5. College of Opto-electronic Engineering, Chongqing University, Chongqing 400044, China;6. College of Mechanical and Electrical Engineering, Hohai University, Changzhou 213022, China;7. Department of Mechanical Engineering, Lamar University, Beaumont, TX, USA;1. Department of Electrophysics, National Chiao Tung University, Hsinchu 300, Taiwan, ROC;2. Department of Mechanical Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, ROC;3. Department of Mechanical Engineering, National Chung Cheng University, Chia-Yi 621, Taiwan, ROC;4. Research Group of Biomedical Image Processing, Shing-Tung Yau Center, National Chiao Tung University, Hsinchu 300, Taiwan, ROC;5. Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, ROC;6. Material and Design Engineering Division Engineering Center, Siliconware Precision Industries Co., Ltd., Taichung 400, Taiwan, ROC;7. Department of Mechatronic Engineering, National Taiwan Normal University, Taipei City 106, Taiwan, ROC;1. Department of Manufacturing and Materials Engineering, University of Campinas, UNICAMP, 13083-860 Campinas, SP, Brazil;2. Federal Institute of Education, Science and Technology of Pará, IFPA, 66093-020 Belém, PA, Brazil |
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| Abstract: | Due to the continuous reduction of the transistor size in electronic devices, it is becoming more and more likely for an SEU (Single Event Upset) to provoke a flip on two or more memory cells in SRAM based FPGAs, which is called a MCU (Multiple Cell Upset). Fault injection in the configuration memory of these devices has been used for many years, in order to evaluate their reliability. Emulation of these injections using the bitstream file has always been a simple, fast and cheap solution. Most of the existent SEU emulation tools do not consider the injection of MCUs, and they do not discuss the implication MCUs have on the overall failure rate of the system.In this work, bitstream based SEU emulators are updated to consider MCUs. It is discussed the necessity of injecting faults on physically adjacent cells, in order to emulate appropriately the effect of MCUs. Adjacent MCU injection has been compared theoretically with an approach considering MCUs as bunches of independent SBUs, as it is done in other emulation platforms. A Zynq-based fault injection platform has been used, in order to apply this way of emulating MCUs and validate the proposal. |
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