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Aging comparative analysis of high-performance FinFET and CMOS flip-flops
Affiliation:1. Department of Applied Physics, Indian Institute of Technology (ISM) Dhanbad, 826004, India;2. Inter University Accelerator Centre, Aruna Asaf Ali Marg, New Delhi 110067, India;1. Department of Electrical Engineering, Motilal Nehru National Institute of Technology (MNNIT), Allahabad, India;2. Department of Electrical and Electronics Engineering, University of Johannesburg, Auckland Park, Johannesburg, South Africa;3. Center for Advanced Life Cycle Engineering (CALCE), University of Maryland, College Park, MD, USA;4. Technology Development Group, Power Grid Corporation of India Limited, Gurgaon, Haryana, India;1. Corporate Reliability Department, Infineon Technologies AG, Am Campeon 1-12, 85579 Neubiberg, Germany;2. Design Enabling and Services Department, Infineon Technologies AG, Am Campeon 1-12, 85579 Neubiberg, Germany;1. Microelectronics Center, Harbin Institute of Technology, Harbin 150001, China;2. Universidad Antonio de Nebrija, C/Pirineos, 55, E-28040 Madrid, Spain
Abstract:This paper presents a comparative performance analysis to investigate the impact of aging mechanisms on various flip-flops in CMOS and FinFET technologies. We consider Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) effects on the robustness of high performance flip-flops. To apply BTI and HCI aging mechanisms, we utilize long-term model to estimate ∆ Vth and employ the updated Vth in transistor model file. The simulation results on performance analysis indicate the high ranking of various flip-flops considering speed and power consumption in each CMOS and FinFET technologies, moreover, approve the superiority of static FinFET flip-flops over CMOS flip-flops. In addition, a comparative analysis considering temperature and VDD variations over different FinFET flip-flop structures demonstrates the average percentages of TDQmin and PDP degradation against aging mechanisms are significantly less than similar CMOS flip-flops.
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