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Interface traps effect on the charge transport mechanisms in metal oxide semiconductor structures based on silicon nanocrystals
Affiliation:1. Laboratoire de Micro''électronique et Instrumentation (LR13ES12), Faculté des Sciences de Monastir, Avenue de l''environnement, Université de Monastir, 5019 Monastir, Tunisia;2. Institut des Nanotechnologies de Lyon - site INSA de Lyon, UMR CNRS 5270, Bât. Blaise Pascal, 7 Avenue Jean Capelle, 69621 Villeurbanne Cedex, France;1. Mechanical Engineering Department, University of Maryland College Park, MD 20742, USA;2. Mechanical and Aerospace Engineering, Seoul National University, Republic of Korea;3. Package Development Team, Semiconductor R&D Center, Samsung Electronics, Republic of Korea;1. Division of Materials Science & Engineering, Hanyang University, Seoul 133-791, Republic of Korea;2. Division of Nanoscale Semiconductor Engineering, Hanyang University, Seoul 133-791, Republic of Korea;3. Department of Chemistry, Hanyang University, Seoul 133-791, Republic of Korea;1. Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, 841 04 Bratislava, Slovakia;2. Department of Physics, University of Central Florida, Orlando, FL 32816-2385, USA;3. Graduate Institute of Electro-Optical Engineering, Chang Gung University, Tao-Yuan 333, Taiwan;4. Institute of Electro-Optical Engineering, Green Technology Research Center, Chang Gung University, Tao-Yuan 333, Taiwan;5. Ming Chi University of Technology, New Taipei City 243, Taiwan;6. Department of Otolaryngology Head and Neck Surgery, Chang Gung Memorial Hospital, Taoyuan 333, Taiwan;1. Department of Manufacturing and Materials Engineering, University of Campinas, UNICAMP, 13083-860 Campinas, SP, Brazil;2. Federal Institute of Education, Science and Technology of Pará, IFPA, 66093-020 Belém, PA, Brazil
Abstract:The transport phenomena in Metal-Oxide-Semiconductor (MOS) structures having silicon nanocrystals (Si-NCs) inside the dielectric layer has been investigated by high frequency Capacitance-Voltage (C-V) method and the Deep-Level Transient Spectroscopy (DLTS). For the reference samples without Si-NCs, we observe a slow electron trap for a large temperature range, which is probably a response of a series electron traps having a very close energy levels. A clear series of electron traps are evidenced in DLTS spectrum for MOS samples with Si-NCs. Their activation energies are comprised between 0.28 eV and 0.45 eV. Moreover, we observe in this DLTS spectrum, a single peak that appears at low temperature which we attributed to Si-NCs response. In MOS structure without Si-NCs, the conduction mechanism is dominated by the thermionic fast emission/capture of charge carriers from the highly doped polysilicon layer to Si-substrate through interface trap-states. However, at low temperature, the tunneling of charge carriers from highly Poly-Si to Si-substrate trough the trapping/detrapping mechanism in the Si-NCs contributed to the conduction mechanism for MOS with Si-NCs. These results are helpful to understand the principle of charge transport of MOS structures having a Si-NCs in the SiOx = 1.5 oxide matrix.
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