基于FPGA的数字相位展开技术研究

针对相位展开软件算法运算复杂的缺点，通过分析相位展开原理，提出基于FPGA的相位展开技术的硬件实现。采用加/减模块、乘法器以及除法器构成截断相位处理模块，将软件算法查找链表的思路转换成RAM存储器读写操作，利用状态机完成对存储器和截断相位处理模块的控制。采用ALTERA 系列EP4CE115F29C7芯片，针对256*256和512*512的图像实现设计，最高工作频率分别达到80.22MHZ，80.45MHZ；资源消耗分别为792和1436个LE。采用SignalTap II Logic Analyzer工具实时验证了相位展开设计模块的正确性。

The study of digital phase unwrapping technique based on FPGA

Since the computation of phase unwrapping algorithm is complex by using software, the hardware circuit of the phase unwrapping technique was designed on the basis of FPGA through the principle of phase unwrapping.The plus/minus module,the multiplier and divider module formed the wrappedphase processing module.The software algorithm to the look-up table changed into the read-write operations of RAM memory.The state machine was used for the control of the memorys and the wrappedphase processing module. The Altera chip of EP4CE115F29C7 was used in this design and the hardware implementation was completed for both 256 * 256 and 512*512 of the image.The highest working frequency reached to 80.22 MHZ and 80.45 MHZ, respectively.The amount of the resource usage reached to 792 and 1436 LEs, respectively. The SignalTap II Logic Analyzer has verified the correctness of the phase unwrapping module realtimely.