CMOS delay time model based on weighted peak current |
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Authors: | Kim KH Park SB |
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Affiliation: | Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul; |
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Abstract: | The authors propose a new CMOS delay time model with the configuration ratio, the input slope and the load condition taken into account. This model is based on the optimally weighted switching peak current. The delay equations are computationally effective and the error is typically within 10% of SPICE results |
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