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A power-aware code-compression design for RISC/VLIW architecture |
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| Authors: | Che-Wei LIN Chang Hong LIN Wei Jhih WANG |
| Affiliation: | Department of Electronic Engineering, National Taiwan University of Science and Technology, Taiwan 106, Taipei |
| Abstract: | |
| Keywords: | LZW compression Cell-based libraries Instruction level parallelism (ILP) VLIW processors |
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