An Evaluation of the CMOS Technology Roadmap From the Point of View of Variability, Interconnects, and Power Dissipation

In this paper, using the new generation of model for assessment of CMOS technologies and roadmaps software, we discuss the CMOS logic roadmap in terms of circuit performance, power dissipation, and variability, such as loaded ring-oscillator delay, as well as through 6T-SRAM functionality. It is shown that these criteria will have to be taken into account in addition to the traditional 17%-per-year delay improvement to construct a new industrially viable roadmap.