多元LDPC译码器设计

在多元低密度奇偶校验码(NB-LDPC)的扩展最小和译码算法（EMS）中，由于消息向量的递归计算和校验/变量节点信息之间的迭代交换，导致译码器存在较大延迟。针对此问题本文提出了一种新型译码器结构，它优化了校验节点更新单步运算单元，根据前向后向算法规则，以3路单步运算单元完成校验节点更新，硬件资源消耗略有增加，但所需时钟周期约降为一般结构的1/3；并采用全并行运算的变量节点信息更新单元，无需利用前向后向算法将更新过程分解为多个单步运算，消除了变量节点更新的递归计算，且具有低复杂度低延时等优点，并在现场可编程门阵列(FPGA)Xilinx Virtex-4 (XC4VLX200)平台上对一个GF(16)域上(480,360)的准循环多元LDPC码进行了综合仿真。仿真结果证明，设计的译码器在较小资源消耗条件下能成倍提高吞吐量。 

A study of the Design of Non-binary LDPC Decoder

This paper addresses decoder design for nonbinary quasicyclic LDPC(QC-LDPC) codes based on the extended min-sum(EMS) algorithm.It is necessary to perform quantities of recursive computation among the message vector,and only one single step operations is utilized to complete the check node update,which leads to larger decoder latency.In this paper,the novel non-binary LDPC decoder architecture is proposed to overcome this problem.Based on the rules of forward-backward algorithm,we utilize three single step operations to complete the check node update and optimize the check node update step operation.The hardware resource consumption for check node update increases slightly,but the cycle required is reduced to 1/3 of general decoder structure.The variable node update unit with fully parallel computation is presented without forward-backward,which removes recursive computation among the message vector and is of low complexity and latency.Moreover,an FPGA implementation for a(480,360) nonbinary QC-LDPC code decoder over GF(16) is designed to demonstrate the efficiency of the presented techniques.Simulation results show that the proposed design scheme can triple throughput of the decoder at the cost of less hardware resource consumption.