Precharged CMOS quaternary logic encoder-decoder circuits

Multiple-valued buses have been proposed as a way of overcoming the interconnection complexity of VLSI. In this paper we present efficient new encoder-decoder circuits for four-valued bus signalling in clocked CMOS VLSI systems. The important advantages of our designs are that they can be implemented by standard binary CMOS processes, and are considerably simpler than earlier designs. Furthermore, they have no static power dissipation. The circuits have been extensively simulated using SPICE and have been found to operate reliably.