Design techniques for high-speed multirate multistage FIR digital filters |
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Authors: | M-C Lin H-Y Chen S-J Jou |
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Affiliation: | 1. Dept. of Electrical Engineering , National Central University , Jhongli, 320, Taiwan, ROC mclin@ee.ncu.edu.tw;3. Dept. of Electronics Engineering , National Chiao Tung University , Hsinchu, 300, Taiwan, ROC |
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Abstract: | This paper presents architecture design techniques for implementing both single-rate and multirate high-speed finite impulse response (FIR) digital filters, with emphasis on the multirate multistage interpolated FIR (IFIR) digital filters. Well-known techniques to achieve high-speed and low-power applications for the single-rate digital FIR architecture are summarized, followed by the introduction of variable filter order selection, optimal filter decomposition, memory-saving and mirror symmetric filter pairs techniques which offer further gains in both performance and complexity reduction for the multirate multistage digital FIR architecture. A filter design example with TSMC 0.25?µm standard cell for 64-QAM baseband demodulator shows that the area is reduced by 39% for low-complexity application. Moreover, for high-speed application, the chip can operate at 714?MHz. Finally, a designed decimator which is used in the CDMA cellular shows that the area is reduced by 70% as compared with conventional approach. |
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Keywords: | FIR digital filter Multirate Interpolated FIR filter |
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