BIST test pattern generator for delay testing |
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| Authors: | Girard P. Landrault C. Moreda V. Pravossoudovitch S. |
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| Affiliation: | Lab. d'Inf. de Robotique et de Microelectron., CNRS, Montpellier; |
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| Abstract: | To detect delay faults in a digital circuit requires a test sequence applied at the nominal frequency of the circuit. Built-in self-test (BIST) is a technique that provides such testing possibilities at speed, without expensive test equipments. A BIST test pattern generator (TPG) design, targeting the detection of delay faults is proposed |
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