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深亚微米CMOS混合信号电路衬底噪声耦合宏模型
引用本文:吴晓鹏,杨银堂,朱樟明.深亚微米CMOS混合信号电路衬底噪声耦合宏模型[J].微电子学与计算机,2006,23(5):128-131,135.
作者姓名:吴晓鹏  杨银堂  朱樟明
作者单位:西安电子科技大学微电子所,陕西,西安,710071
基金项目:中国科学院资助项目;国家科技攻关项目;国家重点实验室基金
摘    要:提出了一种基于二维器件模拟的深亚微米工艺外延型衬底的电阻宏模型.该宏模型通过器件模拟与非线性拟合相结合的方法建立,使衬底寄生参数的提取更加方便,同时保障了深亚微米电路特性的模拟精度.此外,该宏模型结构简单,可以得到与器件模拟基本一致的模拟结果,并可以方便地嵌入SPICE中进行一定规模的电路模拟.

关 键 词:衬底噪声  数模混合电路  电阻宏模型
文章编号:1000-7180(2006)05-004
收稿时间:2005-11-28
修稿时间:2005-11-28

The Substrate Noise Coupling Resistance Macromodel for Deep-submicron CMOS Mixed-Signal ICs
WU Xiao-peng,YANG Yin-tang,ZHU Zhang-ming.The Substrate Noise Coupling Resistance Macromodel for Deep-submicron CMOS Mixed-Signal ICs[J].Microelectronics & Computer,2006,23(5):128-131,135.
Authors:WU Xiao-peng  YANG Yin-tang  ZHU Zhang-ming
Abstract:A resistance macromodel for deep-submicron process epi-type substrate based on the 2D device simulation is presented. The macromodel is built up with the combination of device simulation and nonlinear curve fit, which makes the extraction of the substrate parasitic parameters more convenient and the circuit simulation more accurate. Furthermore, its circuit structure is simple and it can be implemented easily in SPICE program for circuit simulations.
Keywords:CMOS
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