On high-speed computing with a programmable linear array |
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Authors: | Peizong Lee Zvi M Kedem |
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Affiliation: | (1) Institute of Information Science, Academia Sinica, Taipei, Taiwan, R.O.C.;(2) Computer Science Department, Courant Institute of Mathematical Sciences, New York University, 251 Mercer Street, 10012-1185 New York, NY, USA |
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Abstract: | It has been observed by many researchers that systolic arrays are very suitable for certain high-speed computations. Using a formal methodology, we present a design for a single simple programmable linear systolic array capable of solving large numbers of problems drawn from a variety of applications. The methodology is applicable to problems solvable by sequential algorithms that can be specified as nested for-loops of arbitrary depth. The algorithms of this form that can be computed on the array presented in this paper include 25 algorithms dealing with signal and image processing, algebraic computations, matrix arithmetic, pattern matching, database operations, sorting, and transitive closure. Assuming bounded I/O, for 18 of those algorithms the time and storage complexities are optimal, and therefore no improvement can be expected by using dedicated special-purpose linear systolic arrays designed for individual algorithms. We also describe another design which, using a sufficient large local memory and allowing data to be preloaded and unloaded, has an optimal processor/time product.An earlier version of this paper was presented at Supercomputing '88.This work was partially supported by ONR under the contract N00014-85-K-0046 and by NSF under Grant Number CCR-8906949. |
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Keywords: | Parallel processing Programmable systolic array VLSI signal and image processing algebraic computations matrix arithmetic pattern matching database operations sorting transitive closure nested loop algorithms algorithm transformations |
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