| 钝化层沉积工艺对过孔尺寸减小的研究 |
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| 引用本文： | 李田生,谢振宇,张文余,阎长江,徐少颖,陈旭,闵泰烨,苏顺康.钝化层沉积工艺对过孔尺寸减小的研究[J].液晶与显示,2012,27(4):493-498. |
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| 作者姓名： | 李田生 谢振宇 张文余 阎长江 徐少颖 陈旭 闵泰烨 苏顺康 |
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| 作者单位： | 北京京东方光电科技有限公司,北京,100176 |
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| 基金项目： | 京东方研发基金(10SVHM) |
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| 摘 要： | 为了适应TFT-LCD小型化与窄边框化以及在面板布线精细化的趋势,提高工艺设计富裕量以及增加面板的实际利用率,研究了通过改变钝化层(PVX)的沉积工艺来减小液晶面板阵列工艺中连接像素电极与漏极的过孔(VIA)尺寸的方案,通过设计实验考察了影响过孔大小的钝化层的主要影响因素(黑点、倒角、顶层钝化层沉积厚度,顶层钝化层沉积压力),得出了在不改变原有刻蚀方式基础之上使过孔的尺寸降低20%～30%的优化方案,并对其进行了电学性能评价(Ion:开态电流、Ioff:关态电流、Vth:阈值电压、Mobility:迁移率),从而获得了较佳的减小过孔尺寸的方案,提高了产品品质。
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| 关 键 词： | 钝化层 刻蚀 过孔 |
| 收稿时间： | 2012/2/14 |
Improvement Research of VIA Hole Minimize by Passivation Layer Deposit Conditions |
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| LI Tian-sheng
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XIE Zhen-yu
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ZHANG Wen-yu
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YAN Chang-jiang
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XU Shao-ying
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CHEN Xu
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MIN Tai-ye
,
SU Shun-kang.Improvement Research of VIA Hole Minimize by Passivation Layer Deposit Conditions[J].Chinese Journal of Liquid Crystals and Displays,2012,27(4):493-498. |
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| Authors: | LI Tian-sheng XIE Zhen-yu ZHANG Wen-yu YAN Chang-jiang XU Shao-ying CHEN Xu MIN Tai-ye SU Shun-kang |
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| Affiliation: | (Beijing BOE Optoelectronics Technology Co.,Ltd,Beijing 100176,China) |
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| Abstract: | In the trend of miniaturization narrow frame and fine wiring structure,the TFT-LCD tends to developing for large margin of design and high real substrate utilization rate.The passivation layer deposit parameters were changed to decrease the size of via hole which connected the pixel electrode and drain electrode were studied.Through the experiments design of changing main parameters to minimize via hole of passivation layer(haze,undercut,Top-PVX deposit thickness,Top-PVX deposit pressure),a solution to minimize the via hole about 20%~30% without changing the etch conditions was found.The electronic parameter measurement was evaluated(Ion,Ioff,Vth,Mobility) and finally one better solution to minimize via hole size was obtained.Therefore,the products quality was improved also. |
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| Keywords: | passivation layer etch VIA hole |
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