多位并行MQ编码的VLSI结构研究

MQ编码算法的高复杂度,低吞吐率严重制约其应用.本文在分析连续码流编码更新规律的基础上,利用滑动窗口机制和概率统计规律预测区间变化,减少并行数据间的关联,设计出三种不同并行度的MQ编码VLSI结构.并在FPGA芯片上进行优化实现.实验结果表明,与单输入MQ编码器相比,三种结构能在不影响器件工作频率和编码效率的情况下,不同程度的提高系统的处理速率,为MQ编码的大规模应用提供了广泛的选择空问.

VLSI Architecture of Multi-bit Parallel MQ Coder

MQ encoding algorithm is strictly retained for its high implementation costs and low throughput.This paper predicts the interval variety and reduces the relationship of parallel data by using sliding window mechanism and the law of probability statistic based on the updated principle of continuous coding.Three MQ encoder VLSI architectures of different parallel degrees are implemented for FPGA devices.Experimental results show that compared with the single input MQ encoder,these three architectures can increase processing speed at different levels while the working frequency and the encoding quality are slightly influenced.These novel techniques provide flexible choices for following large-scale application of MQ encoding.