| 基于JESD204B协议支持大/小端模式的加扰器 |
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| 引用本文： | 姚佳,蒲杰,何基,吴燕青.基于JESD204B协议支持大/小端模式的加扰器[J].微电子学,2019,49(5):637-642. |
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| 作者姓名： | 姚佳 蒲杰 何基 吴燕青 |
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| 作者单位： | 重庆邮电大学 光电工程学院, 重庆 400065;模拟集成电路国家重点实验室, 重庆 400060,模拟集成电路国家重点实验室, 重庆 400060,重庆邮电大学 光电工程学院, 重庆 400065;模拟集成电路国家重点实验室, 重庆 400060,重庆邮电大学 光电工程学院, 重庆 400065;模拟集成电路国家重点实验室, 重庆 400060 |
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| 基金项目： | 模拟集成电路国家重点实验室基金资助项目(6142802WD201805) |
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| 摘 要： | 设计了一种基于JESD204B协议、支持大/小端模式且具有旁路能力的四字节并行加扰器。在并行加扰/解扰原理的基础上,采用四字节并行处理技术,加快了扰码的产生效率。该加扰器支持大/小端模式,根据不同需求可自行选择不同模式。采用Verilog HDL语言对电路进行设计,利用Modelsim进行功能仿真,在Quartus II软件上进行实现。该加扰器可直接移植到基于JESD204B协议的收发器。
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| 关 键 词： | JESD204B协议 大/小端模式 加扰器 |
| 收稿时间： | 2018/12/16 0:00:00 |
A Scrambler Supporting Big/Little Endian Based on JESD204B Protocol |
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| YAO Ji,PU Jie,HE Ji and WU Yanqing.A Scrambler Supporting Big/Little Endian Based on JESD204B Protocol[J].Microelectronics,2019,49(5):637-642. |
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| Authors: | YAO Ji PU Jie HE Ji and WU Yanqing |
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| Abstract: | A quat-byte parallel scrambler with bypass ability and supported big/little endian was designed based on JESD204B protocol. On the basis of further study of parallel scrambling / descrambling principle, the generation efficiency of scrambling was accelerated by using quat-byte parallel processing technology. At the same time, the scrambler supported big/little endian, and different modes could be selected according to different requirements. The scrambler was designed by Verilog HDL language. The functional simulation was completed by Modelsim, and the circuit was implemented by Quartus II software. It could be transplanted directly into the transceiver circuit based on JESD204B protocol. |
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