嵌入式处理器的浮点乘法器设计

利用阵列乘法器中的压缩部分积的思想,通过对传统的串行执行乘法器的改造,提出了一种带压缩器的串行执行浮点乘法器,分析了具有不同压缩模块结构的乘法器的性能.实验表明,该乘法器可以有效地提高传统的串行乘法器的性能,而面积要小于阵列乘法器.

Design Of Floating-Point Multiplier Used In The Em bedded Processors

This paper presents a cascade floating-point multiplier with compressors by employing the idea of compressing products of multiply and modifying the traditional cascade multiplier. Analyses of several multipliers with different compression architectures are given. The results of experiment shows that the multiplier can improve the performance of the traditional cascade multiplier efficiently, and has less area compared with the array multiplier.