用于RTL设计验证的静态错误检测方法

为快速有效地对集成电路设计中潜在的常见错误进行检测，提出一种基于静态分析的错误检测方法。该方法可以自动地提取待测寄存器传输级(RTL)设计的行为信息，检测出设计中常见的错误，如状态机死锁、管脚配置错误。实验结果表明，静态检测相对于其他验证方法自动化程度高、检测速度快、检测准确度高、检测代码可重用，可以在模拟之前发现设计中的错误。

Static Error Detection Method for RTL Design Verification

For detecting the potential common errors of integrated circuit designs quickly and efficiently, this paper introduces a novel error defection approach based on static analysis. The proposed approach can find errors, such as deadlocks in state machines, errors in pin configuration, by automatically deriving information about the behavior of Register-Transfer Level（RTL） design under verification. Experimental results show that compared with other verification methods, the static method can find errors automatically, efficiently and accurately. It can be reused for any other RTL design to detect errors before simulation.