首页 | 本学科首页   官方微博 | 高级检索  
     

改进型Cordic高精度DDS硬件实现
引用本文:张海涛,苗圃,庞永星,李珍.改进型Cordic高精度DDS硬件实现[J].计算机工程,2011,37(12):230-232.
作者姓名:张海涛  苗圃  庞永星  李珍
作者单位:河南科技大学电子信息工程学院,河南洛阳,471003
基金项目:河南科技大学青年科研基金资助项目
摘    要:针对传统Cordic算法中迭代方向由剩余角度计算结果决定的缺陷,采用一种旋转方向预判断和校模因子改进的方法,在实现并行处理时由输入角二进制各位位值对迭代方向进行预测,可合并部分硬件电路,节省资源,提高算法运行速度和计算精度。实验结果表明,改进后的直接数字频率合成输出信号频谱杂散小且无杂散动态范围提高了20 dB,硬件资源比传统算法节约28%,计算误差达到10-5,该算法在速度、精度和资源低消耗上具有优势。

关 键 词:改进型Cordic  直接数字频率合成  循环迭代  方向预测  现场可编程门阵列

Hardware Implementation of Improved Cordic High Accuracy DDS
ZHANG Hai-tao,MIAO Pu,PANG Yong-xing,LI Zhen.Hardware Implementation of Improved Cordic High Accuracy DDS[J].Computer Engineering,2011,37(12):230-232.
Authors:ZHANG Hai-tao  MIAO Pu  PANG Yong-xing  LI Zhen
Affiliation:(College of Electronic Information Engineering,Henan University of Science & Technology,Luoyang 471003,China)
Abstract:The direction of iterating is decided by the remaining angle results, taking the imported way of pre-determined of the direction of rotating and model factor, achieving the pre-determined of the iteration with the angle' binary code, merging some of the hardware circuits and saving resources, improving the algorithm's speed and accuracy. Experimental results show that the Direct Digital Synthesis(DDS) output signal spectrum spur is small and the Spurious Free Dynamic Range(SFDR) is improved by 20 dB, the hardware resources are saved by 28%, calculation error reaches 10-5 and effectiveness of these methods in speed, accuracy and low consumption is shown.
Keywords:improved Cordic  Direct Digital Synthesis(DDS)  loop iteration  direction prediction  Field Programmable Gate Array(FPGA)
本文献已被 CNKI 维普 万方数据 等数据库收录!
点击此处可从《计算机工程》浏览原始摘要信息
点击此处可从《计算机工程》下载全文
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号