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基于ARM和FPGA高速1553B总线测试系统的设计
引用本文:张玉福,刘鹏,王晓曼.基于ARM和FPGA高速1553B总线测试系统的设计[J].长春理工大学学报,2016,39(5).
作者姓名:张玉福  刘鹏  王晓曼
作者单位:长春理工大学 电子信息工程学院,长春,130022;长春理工大学 电子信息工程学院,长春,130022;长春理工大学 电子信息工程学院,长春,130022
摘    要:鉴于传统的1553B总线设备传输速率低、接口单一化等不能满足实际应用需求的问题,利用Zynq-7000芯片设计一套基于嵌入式ARM控制器和FPGA的高速1553B总线测试系统.采用自顶向下的设计方法,对ARM(PS部分)、FP-GA(PL部分)分别进行设计.PS部分采取USB和以太网双接口完成跟PC机的数据通信;设计IP核实现符合1553B总线协议的编解码处理功能.通过Xilinx自带仿真工具ISE Simulator对各个模式下消息传输进行时序仿真,表明系统提高了1553B总线接口传输速度,使得总线设备与PC机通信更加方便满足实际应用.

关 键 词:1553B总线  Zynq-7000  IP核  嵌入式

Design of High Speed 1553B Bus Test System Based on ARM and FPGA
ZHANG Yufu,LIU Peng,WANG Xiaoman.Design of High Speed 1553B Bus Test System Based on ARM and FPGA[J].Journal of Changchun University of Science and Technology,2016,39(5).
Authors:ZHANG Yufu  LIU Peng  WANG Xiaoman
Abstract:In consideration of the problem that the traditional 1553B bus device can not meet the requirements of practi-cal application, such as low transmission rate, single interface and so on. A high speed 1553B bus test system based on embedded ARM controller and FPGA is designed by using Zynq-7000 chip. Using top-down design method, the ARM (PS part) and FPGA (PL part) were designed. The PS part adopts the USB and Ethernet dual interface to complete the data communication with the PC machine. Design the IP core to achieve the 1553B bus protocol coding and decoding processing function. Through the Xilinx comes with simulation tool ISE simulator for each mode message transmission timing simulation, show that the system improves the 1553B bus interface transmission speed, making bus devices and PC communication more convenient to meet the practical application.
Keywords:1553B bus  Zynq-7000  IP core  embedded
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