CAVLC编码算法及高速熵编码器的FPGA实现

H.264视频编码标准在基本档次和扩展档次采用基于上下文的自适应可变长编码(CAVLC)熵编码方法，但标准并未明确规定CAVLC的具体编码方法。从CAVLC的解码原理出发，详细分析H.264视频编码标准中的CAVLC编码算法，提出一种应用于H.264/AVC标准的高速CAVLC编码器方案，设计中综合采用了多时钟域处理技术与并行处理技术，提高了系统的处理性能；通过算术运算替换部分静态码表，降低系统对存储资源的消耗。给出了各个功能模块的详细设计原理与FPGA硬件实现方法。FPGA实验验证表明，该方案编码系统时钟可达107.97MHz，编码时延小于36个时钟周期，能满足对高清、实时应用的编码要求。

CAVLC coding algorithm and FPGA realization of high-speed entropy encoder

Context-Based Adaptive Variable-Length Coding (CAVLC) algorithm was adopted as an entropy coding method in baseline and extended profile of H.264/AVC standard, but the detailed syntax on which was not explicitly stipulated. A profound analysis on the CAVLC coding algorithm of H.264 standard was performed based on the principle of CALVC decoding method. A high-speed and low power-consumption CAVLC coder for H.264/AVC standard was presented according to the former analysis, in which multi-clock domain processing and parallel processing techniques were adopted to improve the performance of the system, and arithmetic were used to replace some static code table to reduce memory consumption. The detailed design and FPGA realization method on each sub-blocks are also concerned. Finally, FPGA verification and realization indicates that the maximum coding system clock can up to 107.97MHz, and the coding delay is less than 36 clock cycles, which can adequately meet the needs of some high-definition and real-time applications.