一种基于格雷码的异步FIFO设计与实现

介绍了FPGA在实现异步FIFO及其在跨时钟域逻辑设计中的应用，并利用Gray码作异步FIFO指针的方法。该FIFO实现方案与使用传统方案相比，避免了亚稳态的出现，性能更稳定。本设计采用Verilog硬件描述语言实现，具有良好的可移植性和设计灵活性。最后，给出了系统的仿真及综合结果。

A Design and Realization of Asynchronous FIFO Based on Gray Code

This paper introduces the technology of asyn- chronous FIFO using FPGA in logic designs across the multi-clock region,and the method of using Gray code as the pointers of asynchronous FIFO.This method can avoid metastability compared to traditional method and get more stable performance.This design realizes with verilog hardware describing language,so it has a good flexibility and portability.Finally,it gives the system sim- ulation and synthesis results.