| A Novel VLSI Architecture for Real-Time Line-Based Wavelet Transform Using Lifting Scheme |
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| 作者姓名： | Kai Liu Ke-Yan Wang Yun-Song Li and Cheng-Ke Wu |
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| 作者单位： | School of Computer Science Xidian University Xi'an 710071，China，National Key Laboratory of Integrated Service Networks Xidian University，Xi'an 710071，China，National Key Laboratory of Integrated Service Networks Xidian University，Xi'an 710071，China，National Key Laboratory of Integrated Service Networks Xidian University，Xi'an 710071，China |
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| 基金项目： | Supported by the National Natural Science Foundation of China under Grant Nos.60532060 and 60507012. |
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| 摘 要： | In this paper, we propose a VLSI architecture that performs the line-based discrete wavelet transform （DWT） using a lifting scheme. The architecture consists of row processors, column processors, an intermediate buffer and a control module. Row processor and Column processor work as the horizontal and vertical filters respectively. Intermediate buffer is composed of five FIFOs to store temporary results of horizontal filter. Control module schedules the output order to external memory. Compared with existing ones, the presented architecture parallelizes all levels of wavelet transform to compute multilevel DWT within one image transmission time, and uses no external but one intermediate buffer to store several line results of horizontal filtering, which decreases resource required significantly and reduces memory efficiently. This architecture is suitable for various real-time image/video applications.
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| 关 键 词： | VLSI 超大规模集成电路 微波传输 处理器 |
| 收稿时间： | 13 July 2006 |
| 修稿时间： | 2006-07-13 |
A Novel VLSI Architecture for Real-Time Line-Based Wavelet Transform Using Lifting Scheme |
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| Kai Liu,Ke-Yan Wang,Yun-Song Li,and Cheng-Ke Wu.A Novel VLSI Architecture for Real-Time Line-Based Wavelet Transform Using Lifting Scheme[J].Journal of Computer Science and Technology,2007,22(5):661-672. |
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| Authors: | Kai Liu Ke-Yan Wang Yun-Song Li Cheng-Ke Wu |
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| Affiliation: | (1) School of Computer Science, Xidian University, Xi’an, 710071, China;(2) National Key Laboratory of Integrated Service Networks, Xidian University, Xi’an, 710071, China |
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| Abstract: | In this paper,we propose a VLSI architecture that performs the line-based discrete wavelet transform (DWT)using a lifting scheme.The architecture consists of row processors,column processors,an intermediate buffer and a control module.Row processor and Column processor work as the horizontal and vertical filters respectively. Intermediate buffer is composed of five FIFOs to store temporary results of horizontal filter.Control module schedules the output order to external memory.Compared with existing ones,the presented architecture parallelizes all levels of wavelet transform to compute multilevel DWT within one image transmission time,and uses no external but one intermediate buffer to store several line results of horizontal filtering,which decreases resource required significantly and reduces memory efficiently.This architecture is suitable for various real-time image/video applications. |
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| Keywords: | line-based wavelet transforms lifting-based VLSI |
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