A Single-Chip MPEG/Audio Decoder LSI Based on a Compact Decoding Algorithm |
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| Authors: | Masahiro Iwadare Hideto Takano Yoshitaka Shibuya Hideki Sakamoto Takeshi Kuwajima Osamu Kitabatake Naoko Kobayashi |
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| Affiliation: | (1) Information Technology Research Labs, NEC, Kawasaki, Japan;(2) ULSI Systems Development Labs, NEC, Kawasaki, Japan;(3) NEC IC Microcomputer Systems, Osaka, Japan;(4) System Micro Division, NEC, Kawasaki, Japan |
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| Abstract: | ![]()
A single-chip decoder LSI is developed for ISO/IEC MPEG (the International Organisation for Standardisation/the International Electrotechnical Commission, Moving Pictures Expert Group) audio. The applicable layers are Layer I and II of MPEG-1 and MPEG-2/Lower-Sampling-Frequency Mode. A fast calculation algorithm, which is also effective for on-chip memory reduction, is incorporated in audio signal synthesis. The reliability in bitstream synchronization is improved by including bitstream inconsistency detection. Bitstream error concealment by repeating previous audio data is supported. The decoding delay is adjustable when an optional external memory is connected to the LSI. |
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