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| 基于FPGA的软硬件协同仿真加速技术 | |
| 引用本文： | 江霞林,周剑扬,杨银涛,林晓立. 基于FPGA的软硬件协同仿真加速技术[J]. 中国集成电路, 2010, 19(8): 30-33 |
| 作者姓名： | 江霞林 周剑扬 杨银涛 林晓立 |
| 作者单位： | 厦门大学,电子工程系,厦门,361005 |
| 摘 要： | 在系统设计中，硬件复杂电路设计的调试与仿真工作对于设计者来说十分困难。为了降低仿真复杂度，加快仿真速度，本文提出利用FPGA加速的思想，实现软硬件协同加速仿真。经过实验，相对于纯软件仿真，利用软硬件协同加速仿真技术，仿真速度提高近30倍，大大缩短了仿真时间。 |
| 关 键 词： | 现场可编程门阵列 软硬件协同仿真 仿真加速 |
FPGA Based Accelerator for Hardware/Software Co-Simulation |
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| JIANG Xia-lin,ZHOU Jian-yang,YANG Yin-tao,LIN Xiao-li. FPGA Based Accelerator for Hardware/Software Co-Simulation[J]. China Integrated Circuit, 2010, 19(8): 30-33 | |
| Authors: | JIANG Xia-lin ZHOU Jian-yang YANG Yin-tao LIN Xiao-li |
| Affiliation: | (Department of Electronic Engineering, Xiamen University, Xiamen 361005) |
| Abstract: | In system deign, debugging for the design becomes increasingly difficult and designers want more efficient and high-performance verification and debugging solutions. As the design becomes larger and more complex, the pure software simulation suffers from the speed problem. In this paper, we present a new debugging methodology： FPGA based accelerator for hardware/software co-simulation. Experimental results show that the performance gain is up to 30 times over the pure software simulation. |
| Keywords: | FPGA Hardware/Software Co-Simulation Simulation Speed-up |
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