高采样率FIR数字滤波器的设计与实现

介绍了在数字算法设计和实现中基于ＦＰＧＡ四输入查找表结构的ＦＩＲ滤波器流水线设计技术，和结合先进的ＥＤＡ软件进行高效设计的方法和途径，给出了设计的仿真结果。该设计能满足高采样率的要求，设计效率高，对ＦＰＧＡ硬件资源的利用高效合理，而且文中提到的基于流水线技术的算法分解方法可推广应用到其它需要高速数字算法实现的领域中，从而充分挖掘和利用ＦＰＧＡ的高速特性。

Design of a High Sampling-Rate FIR Digital Filter and Its Implementation

Pipelining design of FIR filters in digital algorithm design and implementatio n is described based on 4-input look-up table in FPGA's. Results from simul ation of the design are presented. The design is efficient and can satisfy the demand for high sampling rate. The hardware resources of FPGA's are utilized ef ficiently and properly. The algorithm decomposing based on the pipelining techn ique in the work can be used in other circumstances where high speed algorithms are needed.