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A 2.6-GByte/s multipurpose chip-to-chip interface |
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| Authors: | Lau B. Yiu-Fai Chan Moncayo A. Ho J. Allen M. Salmon J. Liu J. Muthal M. Lee C. Nguyen T. Horine B. Leddige M. Kuojim Huang Wei J. Leung Yu Tarver R. Yuwen Hsia Vu R. Tsern F. Haw-Jyh Liaw Hudson J. Nguyen D. Donnelly K. Crisp R. |
| Affiliation: | Rambus, Mountain View, CA; |
| Abstract: | A 2.6 GByte/s megacell that interfaces to single or double byte wide DRAMs or logic chips is implemented using 0.35-0.18 μm CMOS technologies. Special I/O circuits are used to guarantee 800 Mbit/s/pin data rate. Microwave PC board design methodologies are used to achieve the maximum possible interconnect bandwidth |
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