An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB

This paper presents a differential successive approximation register analog-to-digital converter (SAR ADC)with a novel time-domain comparator design for wireless sensor networks.The prototype chip has been implemented in the UMC 0.18-Nμm 1P6M CMOS process.The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz.With the Nyquist input frequency,68.49-dB SFDR,7.97-ENOB is achieved.A simple quadrate layout is adopted to ease the routing complexity of the common-centroid symmetry layout.The ADC maintains a maximum differential nonlinearity of less than 0.08 LSB and integral nonlinearity less than 0.34 LSB by this type of layout.