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100 MHz all-digital delay-locked loop for low power application |
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| Authors: | Bum-Sik Kim Lee-Sup Kim |
| Affiliation: | Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon; |
| Abstract: | An all-digital delay-locked loop (AD-DLL) is proposed for low power application. The AD-DLL saves design time and effort for synthesis. The number of transistors is reduced by 50%, by introducing a dual-clock dual-input data flip-flop and a coarse delay time buffer. The lock indicator enables zero jitter |
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