一款微处理器芯片电源网络的验证及优化

当CMOS工艺进入深亚微米设计阶段,器件密度和时钟频率增加,电源线和地线网络传送的电流也同样增加,导致功率密度的增加,这些都将对电源网络产生不利影响。因此,设计良好的电源网络显得尤为重要。为了确保较短的设计周期以及满足可靠性和可制造性的要求,电源网络的验证及优化已成为整个设计流程中关键的一步。首先介绍了存在于电源网络的欧姆电压效应,并且给出了一款系统芯片的电源网络的验证优化流程,基于此流程进行欧姆压降的分析,在尽量缩小设计周期的考虑下,给出了优化的几个方法,并应用于工程实际,达到了设计要求。

Verification and Optimization of Power Network for a System Chip

As VLSI design goes into Deep Sub-micro CMOS process,signal integrity issues especially IR-Drop have played a key role.To shorten the period of design and to satisfy the need of reliability and manufacturability,verification and optimization of power network has been an indispensable step.This paper firstly introduces the effect of IR Drop,then we address a flow for verification and optimization of power network,using which we analyze a system chip.Then we propose several optimization methods,and using them optimize the Power/Ground network of the same system chip as above mentioned,finally get design closure.