A 16-bit cascaded sigma-delta pipeline A/D converter |
| |
Authors: | Li Liang Li Ruzhang Yu Zhou Zhang Jiabin Zhang Jun'an |
| |
Affiliation: | National Key Laboratory of Analog ICs, The 24th Institute, China Electronics Technology Group Corporation, Chongqing 400060, China |
| |
Abstract: | A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter (ADC) with a low oversampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate, The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35 μm CMOS process and achieves an SNR of 82 dB. |
| |
Keywords: | multi-bit sigma-delta ADC oversampling pipeline digital filter switched capacitor |
本文献已被 万方数据 等数据库收录! |
| 点击此处可从《半导体学报》浏览原始摘要信息 |
|
点击此处可从《半导体学报》下载全文 |