一种高速并串转换控制电路设计

串行接口常用于高速数据传输,实现多路低速并行数据合成一路高速串行数据.设计了一种高速并串转换控制电路,实现在低频时钟控制下,通过内部锁相环(PLL)实现时钟倍频和数据选通信号,最终形成高速串行数据流,实现每5路全并行数据可按照顺序打包并转换为1路高速串行编码,最后通过一个低电压差分信号(LVDS)接口电路输出.该芯片通过0.18 μmCMOS工艺流片并测试验证,测试结果表明在120 MHz外部时钟频率下,该并串转换控制芯片能够实现输出速度600 Mbit/s的高速串行数据,输出抖动特性约为80 ps,整体功耗约为23 mW.

Design of a High Speed Parallel-to-Serial Conversion Control Circuit

Serial interface is widely used in high speed data transmission,which transforms the low speed multi-channel parallel data to the high speed single-channel serial data.A high speed parallel-to-serial conversion control circuit was designed.The multiplying of the clock frequency and the data-select signal were both generated by the in-chip phase lock loop (PLL) under the low clock frequency control.The five lanes paralleled data were packaged into one high speed serial codes lane in sequence.The high speed serial data stream was driven by the low voltage differential signal (LVDS) interface circuit at last.This chip was fabricated in 0.18 μm CMOS process and was verified.The test results show that the parallel-to-serial conversion control chip could generate high speed serial data with the output speed of 600 Mbit/s at the external clock frequency of 120 MHz.The output jitter is about 80 ps and the total power consumption is about 23 mW.