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| FPGA的布线开关和互连线段的优化设计 | |
| 引用本文： | 王春早,张汉富,施亮. FPGA的布线开关和互连线段的优化设计[J]. 电子与封装, 2007, 7(8): 27-29 |
| 作者姓名： | 王春早 张汉富 施亮 |
| 作者单位： | 江南大学信息工程学院,江苏,无锡,214036;江南大学信息工程学院,江苏,无锡,214036;江南大学信息工程学院,江苏,无锡,214036 |
| 摘 要： | 文章以TSMC'0.35μm,三层金属CMOS工艺为基础,对FPGA互连资源中布线开关和互连线段进行了具体分析。研究表明,布线开关中同时混合使用传输门和三态缓冲器以及采用不同逻辑长度的互连线段组合时将会产生较好的面积-延时值。 |
| 关 键 词： | FPGA 布线开关 互连资源 |
| 文章编号： | 1681-1070（2007）08-0027-03 |
| 修稿时间： | 2007-05-28 |
The Optimized Design of Routing Switch and Wire Segment of FPGA |
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| WANG Chun-zao,ZHANG Han-fu,SHI Liang. The Optimized Design of Routing Switch and Wire Segment of FPGA[J]. Electronics & Packaging, 2007, 7(8): 27-29 | |
| Authors: | WANG Chun-zao ZHANG Han-fu SHI Liang |
| Affiliation: | Institute of Information Engineering of Southern Yangtze University, Wuxi 214036, China |
| Abstract: | The routing switch and wire segment of interconnect resource FPGA have been analyzed concretely based on TSMC'0.35μm, three-layer metal CMOS process in this paper. The results show that employ the different logic length wire segmentation distributions and the best mixes of pass transistors and tri-state buffer switches found in this paper bring more area-delay product. |
| Keywords: | FPGA routing switches interconnect resource |
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