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| 数字电路的高层测试技术及其发展 | |
| 引用本文： | 成本茂,王红,邢建辉,杨士元. 数字电路的高层测试技术及其发展[J]. 微电子学, 2006, 36(2): 187-191 |
| 作者姓名： | 成本茂 王红 邢建辉 杨士元 |
| 作者单位： | 清华大学,自动化系,北京,100084 |
| 基金项目： | 国家自然科学基金资助项目(90207016) |
| 摘 要： | 简要介绍了数字VLSI电路高层测试的概念,主要的高层测试方法,高层测试中所采用的故障模型及其与门级stuck-at故障的对应关系;并展望了高层测试技术的发展趋势。 |
| 关 键 词： | 数字电路 VLSI 高层测试 故障模型 可测性设计 测试综合 |
| 文章编号： | 1004-3365（2006）02-0187-05 |
| 收稿时间： | 2005-07-12 |
| 修稿时间： | 2005-07-122005-09-22 |
High-Level Testing of Digital VLSI Circuits and Its Developing Trend |
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| CHENG Ben-mao,WANG Hong,XING Jian-hui,YANG Shi-yuan. High-Level Testing of Digital VLSI Circuits and Its Developing Trend[J]. Microelectronics, 2006, 36(2): 187-191 | |
| Authors: | CHENG Ben-mao WANG Hong XING Jian-hui YANG Shi-yuan |
| Affiliation: | Dept. of Automation, Tsinghua University, Beijing 100084, P. R. China |
| Abstract: | High-level testing of digital VLSI circuits is briefly reviewed.The most important high-level test approaches are described.High-level fault models and its mapping with the stuck-at faults are presented.And finally,the developing trend of high-level testing is discussed. |
| Keywords: | Digital IC VLSI High-level test Fault model Design for testability (DFT) Test synthesis |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ | |