一种18位SAR ADC的设计实现

本文对逐次逼近型模数转换器（SARADC）的结构进行了介绍，并对影响ADC性能的主要因素加以分析。设计了一种基于二进制加权电容阵列的数字校准算法，并运用比较器自动失调校准技术，实现了高性能SARADC的设计。仿真结果表明该设计在120ksps的采样率下精度可达18位。

18 Bit SAR-A/D Converter Employing Correction Techniques

This paper describes the architecture of successive-approximation analog-to-digital converters. Key factors which affect the performance of ADCs are discussed. A digital calibration methodology based on binary-weighted capacitor array and offset auto-correction technique are presented, which improve the performance of ADC. The simulation results show that it achieves 18 bits of resolution at 120ksps sampling rate