一种12位80 MS/s CMOS流水线ADC设计

介绍了一种12 bit 80 MS/s流水线ADC的设计,用于基带信号处理,其中第一级采用了2.5 bit级电路,采样保持级采用了自举开关提高线性,后级电路采用了缩减技术,节省了芯片面积.采用了折叠增益自举运放,优化了运放的建立速度,节省了功耗.芯片采用HJTC0.18μm标准CMOS工艺,1.8 V电压供电,版图面积2.3 mm × 1.4 mm.版图后仿真表明,ADC在8 MHz正弦信号1 V峰值输入下,可以达到11.10 bit有效精度,SFDR达到80.16 dB,整个芯片的功耗为155 mW.

Design of a 12 bit 80 MS/s CMOS Pipelined ADC

The design of a 12 bit 80 MS/s CMOS pipelined ADC was presented for the application of baseband signal processing. A 2.5 bit stage circuit was used in the first stage. Bootstrap switches were used in S/H to improve the linearity of ADC. Stage circuit scaling was used to save area. Folded cascode gain bost amplifier was optimized for fast settling and power saving. This design was implemented in HJTC 0.18 μm standard CMOS process with 1.8 V supply voltage. A 8 MHz, 1 V_(p-p) sine signal was sampled by 80 MHz clock. Post-simulation results show that an ENOB of 11.10 bit and an SFDR of 80.16 dB are achieved. The chip consumes a power of 155 mW.