A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation

Fully integrated voltage regulators with fast transient response and small area overhead are in high demand for on-chip power management in modern SoCs. A fully on-chip low-dropout regulator (LDO) comprised of multiple feedback loops to tackle fast load transients is proposed, designed and simulated in 90?nm CMOS technology. The LDO also adopts an active frequency compensation scheme that only needs a small amount of compensation capacitors to ensure stability. Simulation results show that, by the synergy of those loops, the LDO improves load regulation accuracy to 3???V/mA with a 1.2?V input and 1?V output. For a 100?mA load current step with the rise/fall time of 100?ps, the LDO achieves maximum output voltage drop and overshoot of less than 95?mV when loaded by a 600?pF decoupling capacitor and consumes an average bias current of 408???A. The LDO also features a magnitude notch in both its PSRR and output impedance that provides better suppression upon the spectral components of the supply ripple and the load variation around the notch frequency. Monte Carlo simulations are performed to show that the LDO is robust to process and temperature variations as well as device mismatches. The total area of the LDO excluding the decoupling capacitor is about 0.005?mm². Performance comparisons with existing solutions indicate significant improvements the proposed LDO achieves.