首页 | 本学科首页   官方微博 | 高级检索  
     


A low cost and low power silicon npn bipolar process with NMOS transistors (ADRF) for RF and microwave applications
Authors:O   K. Garone   P. Tsai   C. Dawe   G. Scharf   B. Tewksbury   T. Kermarrec   C. Yasaitis   J.
Affiliation:Dept. of Electr. Eng., Florida Univ., Gainesville, FL, USA;
Abstract:A silicon bipolar process for RF and microwave applications, which features 25-GHz double-polysilicon self-aligned npn bipolar transistors with 5.5-V BV/sub CEO/, optional 0.7-/spl mu/m (L/sub eff/) NMOS transistors with p/sup +/ polysilicon gates for switch applications, lateral pnp transistors, high and low valued resistors, p/sup +/ polysilicon-to-n/sup +/ plug capacitors, and inductors is described. The npn transistors utilize nitride-oxide composite spacers formed using sacrificial TEOS spacers, a process which is simpler than the previously reported composite spacer processes. Use of the composite spacer structure virtually eliminates problems relating to the extrinsic-intrinsic base link-up and reduces plasma induced damage associated with the conventional spacer process. Microwave and RF capabilities of the process up to several GHz are demonstrated by fabricating and characterizing RF amplifiers, low noise amplifiers, and RF switches.<>
Keywords:
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号