| 分片式流处理器上存储系统的设计与实现 |
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| 引用本文： | 汪芳,安虹,徐光,许牧,姚平.分片式流处理器上存储系统的设计与实现[J].计算机工程,2010,36(11):217-220. |
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| 作者姓名： | 汪芳 安虹 徐光 许牧 姚平 |
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| 作者单位： | 1. 中国科学技术大学计算机科学技术学院,合肥,230027
2. 中国科学技术大学计算机科学技术学院,合肥230027;中国科学院计算机系统结构重点实验室,北京100080 |
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| 基金项目： | 国家自然科学基金资助重点项目(60633040, 60736012)；国家“973”计划基金资助项目(2005CB321601)；国家“863”计划基金资助项目(2006AA01A102, 2009AA01Z106)；教育部-英特尔信息技术专项科研基金资助项目(MOE-INTEL-08-07) |
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| 摘 要： | 针对“存储墙”问题，从提高片外带宽使用率的角度出发，为分片式流处理器设计实现数据并行存储系统。该存储系统通过多级调度能有效减少片外访存的次数，降低片外带宽的需求。软件模拟和仿真验证的结果表明，在不同工作负载特征下，通过设计参数的优化选择，该设计能够充分挖掘存储访问的行局部性和体间并行性，从而提高带宽的使用效率。
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| 关 键 词： | 分片式流处理 数据并行存储系 片外带宽 |
Design and Implementation of Memory System for Tiled Stream Processor |
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| WANG Fang,AN Hong,XU Guang,XU Mu,YAO Ping.Design and Implementation of Memory System for Tiled Stream Processor[J].Computer Engineering,2010,36(11):217-220. |
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| Authors: | WANG Fang AN Hong XU Guang XU Mu YAO Ping |
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| Affiliation: | (1. School of Computer Science and Technology, University of Science and Technology of China, Hefei 230027; 2. Key Laboratory of Computer System and Architecture, Chinese Academy of Sciences, Beijing 100080) |
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| Abstract: | Aiming at the consideration of improving the utilizing efficiency of off-chip bandwidth and resolving ＂Memory Wall＂ problem, this paper designs a Data-Parallel Memory System（DPMS） for the tiled stream processor in current project. This memory system can reduce the time costs of off-chip memory access and meet the needs of off-chip bandwidth. Results of software simulation and emulation verification indicate that for different workloads, the design can fully capture the row-locality and bank-parallelism of memory access, by optimizing the configuration parameters and further boost the utilizing efficiency of DRAM bandwidth. |
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| Keywords: | tiled stream processor Data-Parallel Memory System(DPMS) off-chip bandwidth |
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