| 一种高性能CMOS采样/保持电路 |
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| 引用本文： | 刘民杰,池保勇,刘云峰,董景新. 一种高性能CMOS采样/保持电路[J]. 微纳电子技术, 2009, 46(11). DOI: 10.3969/j.issn.1671-4776.2009.11.012 |
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| 作者姓名： | 刘民杰 池保勇 刘云峰 董景新 |
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| 作者单位： | 1. 清华大学,精密仪器与机械学系,精密测试技术及仪器国家重点实验室,北京,100084
2. 清华大学,微电子研究所,北京,100084 |
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| 基金项目： | 国家十一五预研基金资助项目 |
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| 摘 要： | 提出了一种高性能CMOS采样/保持电路,它采用全差分电容翻转型的主体结构有效减小了噪声和功耗。在电路设计中提出了新型栅源电压恒定的自举开关来极大减小非线性失真,并同时有效抑止输入信号的直流偏移。该采样/保持电路采用0.18μm1P-6M CMOS双阱工艺来实现,在1.8V电源电压、32MHz采样速率下,输入信号直到奈奎斯特频率时仍能达到86.88dB的无杂散动态范围(SFDR),电路的信号噪声失真比(SNDR)为73.50dB。最后进行了电路的版图编辑,并对样片进行了初步测试,测试波形表明,电路实现了采样保持的功能。
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| 关 键 词： | 互补型金属氧化物半导体 采样/保持电路 电容翻转结构 栅压自举开关 跨导放大器 |
A High Performance CMOS Sample and Hold Circuit |
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| Liu Minjie,Chi Baoyong,Liu Yunfeng,Dong Jingxin. A High Performance CMOS Sample and Hold Circuit[J]. Micronanoelectronic Technology, 2009, 46(11). DOI: 10.3969/j.issn.1671-4776.2009.11.012 |
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| Authors: | Liu Minjie Chi Baoyong Liu Yunfeng Dong Jingxin |
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| Abstract: | A high performance sample and hold circuit with the full differential capacitor flip-around architecture,which decreased the noise and power consumption efficiently,was presented.In the circuit design,the new gate voltage bootstrapped switch for constant Vgs was used to reduce significantly nonlinear distortion,and DC drift of the input signal was effectively rejected.It was implemented by 0.18 μm 1P-6M CMOS twin-well process,and an 86.88 dB spurious-free dynamic range(SFDR)and a 73.50 dB peak signal-to-noise plus distortion ratio(SNDR)over the first Nyquist band were obtained with a sampling rate of 32 MHz and a single 1.8 V power supply.Finally,the layout of the circuit and first test waveform of the chip were presented.The result shows the circuit realizes the function of sample and hold. |
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| Keywords: | CMOS sample-and-hold circuit capacitor flip-around architecture bootstrapped switch transconductance amplifier |
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