低功耗低电源线噪声纳米CMOS全加器

提出一种低功耗低电源线噪声的纳米CMOS全加器。采用电源门控结构的全加器来降低纳米CMOS电路的漏电功耗,改进了传统互补CMOS全加器的求和电路,减少了所需晶体管的数目,并进一步对休眠晶体管的尺寸和全加器的晶体管尺寸进行了联合优化。用Hspice在45nmCMOS工艺下的电路仿真结果表明,改进后的全加器电路在平均功耗时延积、漏电功耗和电源线噪声等方面取得了很好的效果。

Low Power and Low Ground Bouncing Noise Nanometer CMOS Full Adder

A low power and low ground bouncing noise nanometer CMOS full adder is presented.The full adder with power gating structure is used to reduce leakage power consumption.The sum generator circuit of complementary CMOS full adder is modified and the transistor counts are reduced.Sizing of the sleep transistor and the transistors for the full adder is done.The proposed full adder is simulated using 45nm CMOS technology and the simulation results demonstrate better improvements in average power-delay product,leakage power consumption and grounding bouncing noise.