一种VLSI设计到赋权超图的转换系统

本文基于VLSI划分问题的需要,提出了一种VLSI设计到赋权超图转换算法.该算法解决的关键问题是,它读取和遍历Verilog语言描述的树状结构VLSI设计,将其转换为赋权超图并存储为指定的文件存储格式,从而有效地将VLSI划分问题转换为超图划分优化问题.进而,本文给出了VLSI设计到赋权超图的转换系统（VLSI/Hypergraph Converter,VHC）的处理流程图,并在Windows平台下用C＋＋设计实现了VHC系统.实验及分析表明,该系统能正确地将Verilog语言描述的门级CPU测试用例转换为赋权超图,避免了直接在VLSI线网上进行划分,提高了VLSI划分的效率.

An Effective Converter to Translate VLSI Design into Hypergraph

We propose an effective algorithm for converting VLSI design into weighted hypergraph which converts the VLSI partitioning problem into the hypergraph partitioning problem.The algorithm reads and traverses the hierarchical VLSI design of verilog language,converts the VLSI design into the compressed storage format(CSF) of hypergraph and saves as file storage format(FSF) of hypergraph.Furthermore,a VLSI/Hypergraph Converter(VHC) is proposed and implemented for VLSI partitioning problem.The VHC’s flow diagram is also presented.Finally,the experiment and analysis show that the VHC can rightly convert the case of gate CPU into FSF of hypergraph and its objective is to improve the efficiency of VLSI partitioner by avoiding partitioning the netlist of VLSI directly.