| 可配置LDPC译码器中低复杂度移位网络的设计 |
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| 引用本文： | 张明瑞,张岩,金杰,杨舜琪. 可配置LDPC译码器中低复杂度移位网络的设计[J]. 微电子学, 2012, 42(3): 363-366 |
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| 作者姓名： | 张明瑞 张岩 金杰 杨舜琪 |
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| 作者单位： | 1. 哈尔滨工业大学 深圳研究生院 网络智能计算重点实验室,深圳,518055
2. 华为技术有限公司,深圳,518129 |
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| 摘 要： | 针对可配置LDPC译码器,提出了一种低复杂度的移位网络结构,明显降低了硬件实现的复杂度。基于结构化LDPC译码器的两个特点:输入端的个数是一个常数的倍数、所有移位都是循环移位,提出易于实现且延迟很小的移位网络控制信号生成算法。此外,针对IEEE 802.16e标准的LDPC译码器,设计了采用这种结构的移位电路。基于SMIC 130nm工艺进行仿真,综合结果表明,该电路占用的芯片面积为0.11mm2,最高频率为430MHz。
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| 关 键 词： | 可配置 移位网络 低密度奇偶校验码 循环移位 |
Design of Low-Complexity Shuffle Network for Reconfigurable LDPC Decoder |
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| ZHANG Mingrui , ZHANG Yan , JIN Jie , YANG Shunqi. Design of Low-Complexity Shuffle Network for Reconfigurable LDPC Decoder[J]. Microelectronics, 2012, 42(3): 363-366 |
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| Authors: | ZHANG Mingrui ZHANG Yan JIN Jie YANG Shunqi |
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| Affiliation: | 1(1.Key Laboratory of Network Oriented Intelligent Computation,Shenzhen Graduate School,Harbin Institute of Technology, Shenzhen 518055,P.R.China;2.Huawei Technologies,Shenzhen 518129,P.R.China) |
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| Abstract: | A low-complexity shuffle network was proposed for reconfigurable LDPC decoders.Using the proposed architecture,the complexity of hardware implementation could be significantly reduced.Based on two properties that the input number is a multiple of a certain number and only cyclic shift is required in structured LDPC decoders,an efficient algorithm was also proposed to generate control signals for all switch units in the network,which could be easily implemented with small latency.Furthermore,a shuffle network for IEEE 802.16e LDPC decoders was presented based on the proposed architecture.Simulation was made based on SMIC’s 130 nm process.Synthesis results showed that the proposed shuffle network had a maximum operating frequency of 430 MHz,and it occupied a chip area of only 0.11 mm2. |
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| Keywords: | Configurable Shuffle network LDPC Cyclic shift |
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