Scaling trends of power noise in 3-D ICs |
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| Affiliation: | 1. PGMicro - UFRGS, Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil;2. IBM Research, Austin, TX, United States;3. PGMicro/PPGC - UFRGS, Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil;1. National Laboratory of Solid State Microstructures, Jiangsu Provincial Key Laboratory for Nano Technology, School of Physics, Nanjing University, Nanjing 210093, China;2. School of Physical and Mathematical Sciences, Nanjing Tech University, Nanjing 211816, China;3. School of Sciences, Nanjing University of Science and Technology, Nanjing 210094, China |
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| Abstract: | Power supply noise in three-dimensional integrated circuits (3-D ICs) considering scaled CMOS and through silicon via (TSV) technologies is the focus of this paper. A TSV and inductance aware cell-based 3-D power network model is proposed and evaluated. Constant TSV aspect ratio and constant TSV area penalty scaling, as two scenarios of TSV technology scaling, are discussed. A comparison of power noise among via-first, via-middle, and via-last TSV technologies with CMOS scaling is also presented. When the TSV technology is a primary bottleneck in high performance 3-D ICs, an increasing TSV area penalty should be adopted to produce lower power noise. As a promising TSV technology, via-middle TSVs are shown to produce the lowest power noise with CMOS technology scaling. |
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| Keywords: | Through silicon vias (TSVs) 3-D integrated circuits (3-D ICs) Inductive coupling Power supply noise Technology scaling |
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