Power supply noise in accurate delay model for the sub-threshold domain |
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| Affiliation: | 1. Department of Computer Science and Technology, Beijing University of Chemical Technology, No.15, Beisanhuan East Road, ChaoYang District, Beijing 100029, China;2. Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China;3. Department of Electronic and Communication Engineering, School of Electrical and Electronic Engineering, North China Electric Power University, Baoding 071003, China;4. School of Computer and Information, Hefei University of Technology, Hefei 230009, China;1. Department of Electrical and Electronic Engineering, Bogazici University, Istanbul, Turkey;2. IMSE, CSIC and University of Seville, Spain;1. Guangzhou Institute of Advanced Technology, CAS, China;2. Shenzhen Institute of Advanced Technology, CAS, China;3. The Chinese University of Hong Kong, China;4. University of Nevada, Las Vegas, United States;5. University of Turku, Finland;6. Royal Institute of Technology, Sweden;1. School of Electrical and Computer Engineering, University of Tehran, Iran;2. School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Iran;3. Department of Electrical Engineering-Systems, University of Southern California, USA |
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| Abstract: | Ultra-Low-Power circuits demand has dramatically increased in the last few years. One of the main challenges in designing these circuits is that transistors often run in the sub-threshold regime and their on current is exponentially dependent on the gate-to-source voltage, thus making sub-threshold gates extremely susceptible to power and ground noise phenomena. This paper provides a complete mathematical model in closed form for the delay of sub-threshold CMOS inverters. The novel model can predict the behavior of inverters output signal and therefore it can be extremely useful in the design phase to analyze the variations caused by noise on the output over/undershoot and the gate delay. The proposed model has a general validity since it considers the ground and supply noises completely uncorrelated both in frequency and in amplitude. When a commercial CMOS 45 nm process technology is referenced, the proposed model exhibits a maximum error of only ~16% under different conditions in terms of output load capacitance, input signal rising/falling time, noise phase and frequency. |
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| Keywords: | Sub-threshold CMOS Propagation delay Power supply noise Analytical model |
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